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Friday 21 November 2008
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|NewsletterMemory
Virage Logic delivers memory for TSMC 65nm process
Thursday 5 April 2007
Virage Logic has delivered first silicon proven memory for TSMC’s 65nm general-purpose plus (GP) process.
The firm is offering customers a test chip based on Virage Logic’s Self-Test and Repair (STAR) SRAM memory IP for embedding in SoCs.
“The availability of Virage Logic’s silicon proven memory on TSMC’s 65nm GP process will facilitate the market’s migration to smaller process nodes,” said Fu-Chieh Hsu, v-p, design and technology platform at TSMC.
According to Dan McCranie, president and CEO of Virage Logic: “Being first to market with silicon proven memory IP for TSMC’s 65nm process underscores this commitment and we are very pleased to expand our collaboration on next generation process technology.”
According to the firms, the sub-90nm collaboration model was created to address the complexities of robust SRAM design from bit-cell design to silicon validation. At 65nm, the STAR Test Chip methodology helps ensure SRAM robustness in a SoC for functionality, performance and yield.
Last month, Altera started sampling customers with its first 65nm Cyclone III devices which were manufactured on TSMC’s low power 65nm process.
The firm is offering customers a test chip based on Virage Logic’s Self-Test and Repair (STAR) SRAM memory IP for embedding in SoCs.
“The availability of Virage Logic’s silicon proven memory on TSMC’s 65nm GP process will facilitate the market’s migration to smaller process nodes,” said Fu-Chieh Hsu, v-p, design and technology platform at TSMC.
According to Dan McCranie, president and CEO of Virage Logic: “Being first to market with silicon proven memory IP for TSMC’s 65nm process underscores this commitment and we are very pleased to expand our collaboration on next generation process technology.”
According to the firms, the sub-90nm collaboration model was created to address the complexities of robust SRAM design from bit-cell design to silicon validation. At 65nm, the STAR Test Chip methodology helps ensure SRAM robustness in a SoC for functionality, performance and yield.
Last month, Altera started sampling customers with its first 65nm Cyclone III devices which were manufactured on TSMC’s low power 65nm process.
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